In digital systems design, the high-speed adders play an essential role in modules like adders, multipliers, division, etc. to obtain the response in quickly. In digital signal processor and computer datapath circuits, carry look-ahead adder (CLA), carry save adder (CSA), carry select adder (CSeA) and carry skip adder are the mostly used fast adders to improve the performance of the system. This work mainly focuses on fault-tolerant carry save adder using hardware redundancy configurations for the betterment of reliability at the cost of the area. The popular methods like dual (DMR) and triple modular redundancy (TMR) are implemented to detect an error and tolerate single event upset (SEU) error respectively. To tolerate multiple errors, for example, two, three and four errors, the 5-modular (quintuple), 7-modular (septuple), and 9-modular (nonuple) redundancy configurations are used respectively. For experimental results, the implementation of a simple addition of four 4-bit numbers is considered on Altera FPGA EP4CE115F29C7 device using Quartus II synthesis software tool. Simulation results reveal that for example in nonuple MR, CSA using CSeA final stage obtain higher performance (45.7 MHz) with moderate power dissipation as 173.36 mW and at the cost of more LEs (216).